課題組目前已承擔(dān)的相關(guān)科研項(xiàng)目包括：
（1）國(guó)家自然科學(xué)基金重點(diǎn)項(xiàng)目子課題“超并行計(jì)算機(jī)體系結(jié)構(gòu)上的多核并行編程模型
和環(huán)境研究”（在研）。
（2）973項(xiàng)目子課題“可重構(gòu)片上并行體系結(jié)構(gòu)”（在研）。
（3）國(guó)家863重大項(xiàng)目子課題“高效能千萬(wàn)億次級(jí)系統(tǒng)上軟硬件協(xié)同支持的程序并行化
方法”（在研）。
（4）總參某部基礎(chǔ)研究項(xiàng)目“面向多核結(jié)構(gòu)的并行算法設(shè)計(jì)與編程方法研究”（在
研）。
（5）教育部-英特爾信息技術(shù)專(zhuān)項(xiàng)科研基金項(xiàng)目“多核結(jié)構(gòu)上軟硬件協(xié)同支持的串行程
序線程化技術(shù)研究” （在研）。
（6）國(guó)家自然科學(xué)基金項(xiàng)目“可擴(kuò)展多線程處理器中的資源共享技術(shù)” （結(jié)題）。
（7）總參某部基礎(chǔ)研究項(xiàng)目“并行理論與方法研究 ” （結(jié)題）。
（7）總參某部基礎(chǔ)研究項(xiàng)目“并行理論與方法研究”（結(jié)題）。
（8）安徽省自然科學(xué)基金項(xiàng)目“多線程多內(nèi)核網(wǎng)絡(luò)處理器體系結(jié)構(gòu)研究”（結(jié)題）。
（9）Intel公司高等教育項(xiàng)目“Efficient Thread-level Speculation and
Transactional Execution Model for CMP” （結(jié)題）。
（10）中科院計(jì)算機(jī)系統(tǒng)結(jié)構(gòu)重點(diǎn)實(shí)驗(yàn)室開(kāi)放課題，片上多處理器結(jié)構(gòu)上的串行程序線
程化研究（結(jié)題）
主要研究問(wèn)題：
(1)Chip Multiprocessor Architecture and Parallel Computer Architecture
One main question facing to modern computer system design is: is it ever
possible to build a high-productivity parallel processing architecture
combining the power efficient or even thousands of processors, to solve real
world applications (regular or irregular) with scalable performance? My
research interests in parallel processing architecture, including chip
multiprocessor architecture and parallel computer architecture, have been
focused on seeking an answer to this challenge. In particular, our current
work has been concentrated on multithreaded program execution models, data-
flow driven program execution models, stream program execution models and
chip multiprocessor architectures which can implement the three program
execution models.
(2)Parallel Programming Models, Tools and Environment
Under this research area my interests are in parallel programming models
and system software design, including program profiling tools, compilers,
runtime software, and programming tools, for high-productivity parallel
processing architectures. My research focus includes system software
techniques for the following architecture models (1) chip multiprocessor
architectures with instruction level parallelism (ILP), using data-flow
driven program execution; (2) stream processor architecture with data level
parallelism(DLP); (3) multiprocessor architectures with thread level
parallelism(TLP). We are interested in both general purpose as well as
embedded systems (including SoCs), and their code optimization for speed,
efficiency, power, code size, etc.